Static random access memory (SRAM) is a type of semiconductor memory that is volatile but static (i.e., does not have to be refreshed periodically, but still loses data when power is removed). Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit. Access to the SRAM bitcell is enabled by a word line which controls two access transistors which, in turn, control whether the cell should be connected to the bit lines. Bit lines are used to transfer data for both read and write operations. More ports can be added to the basic SRAM cell when multiple data needs to be accessed at the same time.
FIG. 1 shows a schematic diagram for a traditional SRAM memory cell implementation with 3 read ports (read ports 0-2). Typically, to determine the address range that each processor or device is mapped to, memory addresses are decoded using decoders (100, 102, 104). Each output of the decoders (100, 102, 104) is sent to the memory bitcell (106) for selection of physical memory addresses. Thus, for example, in FIG. 1, there are three addresses, address0, address1, and address2, each with a common address portion (address_common) that are decoded and sent to the memory bitcell (106). The common address portion is a fixed number of bits of the memory address that are identical in each memory address. The memory bitcell (106) includes three wordlines 0-2 to receive the three decoded memory addresses.
As can be seen in the schematic, the memory bitcell (106) includes bitcell logic (108). The bitcell logic (108) includes the transistors and cross-coupled inverters of a typical SRAM bitcell described above. Using this bitcell logic (108), the memory bitcell (106) is configured to output the physical memory addresses to be read on each of the read ports 0-2. These outputted physical memory addresses are amplified by the local sense amplifier (LSA) (110). Due to large arrays of SRAM memory bitcells, the resulting signal, in the event of a read operation, has a much lower voltage swing. To compensate for that swing the LSA (110) is used to amplify voltage coming out of the read ports (bitlines) of the memory bitcell (106). Thus, the multi-port SRAM of FIG. 1 has three read ports corresponding to the wordlines 0-2 and a common address portion for each of the ports on which memory address data is output.